It is conventional practice in a semiconductor fabrication enterprise to provide test structures, reference elements, or monitoring elements (hereafter all referred to as test structures) on-chip for the purpose of taking parametric and functional measurements. Such measurements may be taken as part of the circuit and process design or as part of a check on process parameters for feedback into the fabrication process as part of an overall production process control strategy. As used herein, chip may refer to a semiconductor wafer or portion thereof of interest in the testing of parametric and/or circuit characteristics. Regions of interest may include particular representative wafer areas, all or select die area, scribe lines or kerfs or other unused wafer portions, etc. Such methodology has become important and commonplace in the development and control of the fabrication process which includes numerous and varied steps and process parameters.
With reference first to FIG. 1 a portion of a semiconductor chip 10 is illustrated having built-in or on-chip test structures 11. Test structures are fabricated during the regular course of process development or production processing utilized to fabricate the desired end product device. These test structures are checked, depending upon test structure, for functional or parametric compliance with desired results. Access for testing is accomplished by expensive, precision probing machinery that steps through the various test structures by contacting probing pads 13. With ever decreasing structure scales and ever increasing device densities which typify the industry, the probing pads have come to undesirably occupy ever increasing proportional areas 15 of the overall wafer floor plan. It is not practical nor cost effective to further miniaturize the external probing machinery and equipment which in turn would allow miniaturization of the contact probing areas on-chip.